Electronic device manufacturers are constantly pursuing ways to reduce the size and increase the operational capabilities of the electronic memory circuits used in modern computing equipment. In memory circuits that include arrays of memory cells, such as dynamic random access memories (DRAMs), for example, the array size is determined in large part by the memory cell and sense amplifier size. Although cell area is decreasing through the use of finer three-dimensional geometries and high dielectric constant storage node materials, the sense amplifier is not getting as small as desired. This is due to the amount of functionality that must be packed into the sense amplifier circuit (amplification, equalization, column select, pre-charge, and share gate devices, along with sense circuitry and supplies), and to the substrate isolation and array to direct periphery (sense amplifier circuit) spacing design rules which make it difficult to shrink the overall circuit.
Several schemes are currently used, or have been proposed, to reduce the sense amplifier portion of the memory array area. One scheme is to increase the number of bits hanging on a bitline to simply reduce the number of sense amplifiers in the array. This has been an effective solution, but since it increases the bitline-to-cell capacitance ratio, the approach adversely affects sensing speed, sensing noise margin, and power. This is due, in large part, to the slower speed and greater current flow that the higher bitline capacitance produces.
Another interesting scheme involves segmenting the bitline with pass gate transistors to increase the bitline length while holding down the bitline capacitance (commonly known as hierarchical bitlines). The purpose of this scheme is to reduce the number of sense amplifiers in the memory array. This method, nonetheless, has several drawbacks. One limitation is the difficulty of fabricating the pass gate structure. Another limitation is the marginal benefit in bitline capacitance reduction. In particular, segmenting the bitline in two parts actually does not result in a fifty percent (50%) reduction in effective bitline capacitance. This is especially true when tighter design rules are employed. In addition, significant sensing and writing speed degradation results from the increase in the number of pass gate transistors in the storage cell to sense amplifier path.
Other schemes to reduce the sense amplifier portion of the memory array area involve brute-force methods such as shrinking the sense amplifier design rules, reducing the bitline capacitance by using lower dielectric materials and shrinking the bitline using low sheet resistance materials (such as TiSi.sub.x, Cu, etc.). These solutions are currently employed in the field or have been proposed to reduce the area the sense amplifiers. However, as the density of memory devices increase, there is still the need for a more robust solution.